Fx2lafw is free firmware for Cypress FX2 chips which makes them usable as simple logic analyzer and/or oscilloscope hardware.

Cocotb-bus provides a set of utilities, test benches and reusable bus interfaces to be used with cocotb.

Pcb-rnd is a Printed Circuit Board layout editor, part of the RiNgDove EDA suite.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

OpenCircuitX is a EDA platform for HDL used to design digital logic. It unifies an IDE HDL editor, a visual circuit canvas, an RTL schematic viewer, a waveform viewer, and a full FPGA toolchain in one window, for hardware engineers, students, and FPGA hobbyists alike.

netgen is a general purpose LVS management tool. It compares netlists of SPICE or verilog netlists circuits. This is commonly used as a part of toolchains in a process called LVS with the intent to verify that the layout of a circuit corresponds to the desired netlists.

Sigrok-cli is a command-line frontend for sigrok.

This package contains the official KiCad footprint libraries.

This package provides a VHDL and SystemVerilog parser library for Python.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

ABC is a program for sequential logic synthesis and formal verification.

Icarus Verilog is a Verilog/SystemVerilog EDA compiler that generates code employed by back-end tools. It operates compiling source code written in Verilog (IEEE-1364) and SystemVerilog (IEEE-1800) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.

This package is a waveform viewer for FST files.

qrouter is an ASICs tool intended for digital chip design. It creates the detailed routes for layouts of digital circuits and generates metal layers and vias.

qucsrflayout command exports RF schematics to KiCad layouts and OpenEMS scripts.

Libfst is a small library used to read and write FST format waveforms.

Route-rnd is a generic external autorouter for PCB using tEDAx file format, part of the RiNgDove EDA suite.

HAL is an EDA comprehensive netlist reverse engineering and manipulation framework. It provides a framework to parse netlists of arbitrary sources, e.g., FPGAs or ASICs, into a graph-based netlist representation, providing the necessary built-in tools for traversal and analysis of the included gates and nets.

Slang is a software library that provides various components for lexing, parsing, type checking, and elaborating SystemVerilog code. It comes with an executable tool that can compile and lint any SystemVerilog project, but it is also intended to be usable as a front end for synthesis tools, simulators, linters, code editors, and refactoring tools.

PyXHDL replaces HDL code by Python, generating VHDL (>= 2008) and Verilog (SystemVerilog >= 2012) code to be used for synthesis and simulation.

python-gdstk is a Python library for creation and manipulation of GDSII layout files which are commonly used for EDA and chip design.

PulseView is a Qt based logic analyzer, oscilloscope and MSO GUI for sigrok.

libpsf is a c++ library that reads Cadence PSF binary waveform files.

Camv-rnd is a viewer for PCB supporting gerber, excellon and g-code. It is part of the RiNgDove EDA suite.