The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as evaluation board definitions and a System on Chip toolkit.

ABC is a program for sequential logic synthesis and formal verification. This is the Yosyshq fork of ABC.

PyUVM is a Python implementation of the UVM, as defined in the IEEE 1800.2 standard. It uses cocotb to interact with simulators and schedule simulation events. It implements the most commonly used sections of the IEEE 1800.2 standard.

OSVVM is a verification methodology that defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability for FPGA or ASIC verification.

Pydigitalwavetools is a Python library to parse, write and format digital wave files in VCD format, a standardized ASCII format used to store simulation data from Verilog and other hardware description languages.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

ciel downloads and installs open-source PDKs which are used for chip design and EDA.

The codePyUCIS library provides two APIs for creating and accessing coverage data via the UCIS data mode.

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

gdstk is a library for creation and manipulation of GDSII layout files which are commonly used for EDA and chip design.

Surfer is a waveform viewer used in EDA with a focus on usability and extensibility.

This package provides a library to turn Python into a hardware description and verification language.

KLayout is EDA software. It is a scriptable VLSI layout editor used for visualizing and editing mask data, transcoding between different file formats (GDSII and OASIS), executing DRC, LVS verification, and drawing of chip cross-sections basked on mask data.

Prjpeppercorn includes programming tools for GateMate architecture from Cologne Chip. It also provides data needed to produce a nextpnr chip database Cologne Chip's GateMate architecture.

Charlib is an EDA tool used to extract timing and power characteristics from CMOS combinational and sequential standard-cells. It is compatible with ngspice and Xyce.

Eqy is an EDA front-end driver program for Yosys-based formal hardware equivalence checking. It performs formal verification on two designs, such as ensuring that a synthesis tool has not introduced functional changes into a design, or ensuring that a design refactor preserves correctness in all conditions.

This is a pythonized, kind of reverse engineered version of original AACircuit written by Andreas Weber in Borland Delphi. The idea and GUI layout are also taken from the original.

Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.

LibreLane is an EDA ASIC infrastructure library based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for design exploration and optimization.

OpenROAD is an EDA toolkit for RTL to GDS design flows. It provides all necessary steps from VLSI designs to implement integrated chip physical designs, from RTL design to synthesized Verilog and routed layout. It includes tools for floorplanning, placement, clock tree synthesis, routing, parasitic extraction, and timing analysis.

fftgen produces FFT hardware designs in Verilog.

This package contains the official KiCad project and worksheet templates.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.